Otawa  0.10
CacheDriver.h
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1 /*
2  * $Id$
3  * Copyright (c) 2007, IRIT-UPS <casse@irit.fr>.
4  *
5  * CacheDriver class interface.
6  */
7 #ifndef OTAWA_SIM_CACHE_DRIVER_H
8 #define OTAWA_SIM_CACHE_DRIVER_H
9 
10 #include <otawa/base.h>
11 
12 namespace otawa {
13 
14 namespace sim {
15 
16 // External classes
17 class State;
18 
19 // CacheDriver class
20 class CacheDriver {
21 public :
22  typedef enum {
23  MISS = 0,
24  HIT = 1
25  } result_t;
26 
27  typedef enum {
30  } action_t;
31 
32  virtual ~CacheDriver(void);
33  virtual result_t access(address_t address, size_t size, action_t action) = 0;
34 
37 };
38 
39 } } // otawa::sim
40 
41 #endif // OTAWA_SIM_CACHE_DRIVER_H
result_t
This enumeration allows to know the result of a cache access.
Definition: CacheDriver.h:22
A read is performed on the cache.
Definition: CacheDriver.h:28
uint32 size
elm::io::IntFormat address(Address addr)
Build a format to display addresses.
Definition: base.cpp:213
static CacheDriver & ALWAYS_MISS
This cache driver specialization generates a miss each time it is accessed.
Definition: CacheDriver.h:36
The result of a cache access produces a miss.
Definition: CacheDriver.h:23
This class provides a simple interface to drive the cache management unit of a simulator.
Definition: CacheDriver.h:20
static CacheDriver & ALWAYS_HIT
This cache driver specialization generates a hit each time it is accessed.
Definition: CacheDriver.h:35
The representation of an address in OTAWA.
Definition: base.h:54
virtual result_t access(address_t address, size_t size, action_t action)=0
This function is called each time the cache is accessed.
A write is performed on the cache.
Definition: CacheDriver.h:29
virtual ~CacheDriver(void)
Definition: sim_CacheDriver.cpp:58
The result of a cache access produces a hit.
Definition: CacheDriver.h:24
action_t
This enumeration identifies the kind of cache access.
Definition: CacheDriver.h:27
action_t
Definition: cfg_DelayedBuilder.cpp:68