Otawa  0.10
Cache.h
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1 /*
2  * $Id$
3  * Cache class interface.
4  *
5  * This file is part of OTAWA
6  * Copyright (c) 2005-11, IRIT UPS.
7  *
8  * OTAWA is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * OTAWA is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with OTAWA; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21  */
22 #ifndef OTAWA_HARD_CACHE_H
23 #define OTAWA_HARD_CACHE_H
24 
25 #include <elm/assert.h>
26 #include <elm/io.h>
27 #include <elm/serial2/macros.h>
28 #include <elm/genstruct/Vector.h>
29 #include <otawa/base.h>
30 
31 namespace otawa { namespace hard {
32 
33 // Cache class
34 class Cache {
35 public:
36  typedef enum replace_policy_t {
37  NONE = 0,
38  OTHER = 1,
39  LRU = 2,
40  RANDOM = 3,
41  FIFO = 4,
42  PLRU = 5
44 
45  typedef enum write_policy_t {
49 
50  typedef struct info_t {
54  int row_bits;
55  int way_bits;
58  bool allocate;
62  } info_t;
63 
64  typedef t::uint32 block_t;
65  typedef t::uint32 set_t;
66  typedef t::uint32 tag_t;
68 
69 private:
71  field("access_time", _info.access_time, 1) &
72  field("miss_penalty", _info.miss_penalty, 10) &
73  field("block_bits", _info.block_bits, 4) &
74  field("row_bits", _info.row_bits, 12) &
75  field("way_bits", _info.way_bits, 0) &
76  field("allocate", _info.allocate, false) &
77  field("next", _next, (const Cache *)0) &
78  field("replace", _info.replace, LRU) &
79  field("write_buffer_size", _info.write_buffer_size, 0) &
80  field("read_port_size", _info.read_port_size, 1) &
81  field("write_port_size", _info.write_port_size, 1) &
82  field("write", _info.write, WRITE_THROUGH));
84  const Cache *_next;
85 
86 public:
87 
88  Cache(void);
89  Cache(const Cache& cache, const Cache *next = 0);
90  virtual ~Cache(void);
91 
92  // Simple accessors
93  inline const Cache *nextLevel(void) const { return _next; }
94  inline ot::size cacheSize(void) const { return 1 << (blockBits() + rowBits() + wayBits()); }
95  inline ot::size blockSize(void) const { return 1 << blockBits(); }
96 
97  inline int wayCount(void) const { return 1 << wayBits(); }
98  inline int setCount(void) const { return 1 << rowBits(); }
99  inline int blockCount(void) const { return 1 << (_info.row_bits + _info.way_bits); }
100 
101  inline replace_policy_t replacementPolicy(void) const { return _info.replace; }
102  inline write_policy_t writePolicy(void) const { return _info.write; }
103  inline bool doesWriteAllocate(void) const { return _info.allocate; }
104  inline int missPenalty(void) const { return _info.miss_penalty; }
105  inline int writeBufferSize(void) const { return _info.write_buffer_size; }
106  inline int readPortSize(void) const { return _info.read_port_size; }
107  inline int writePortSize(void) const { return _info.write_port_size; }
108 
109  // Low-level information
110  inline int blockBits(void) const { return _info.block_bits; }
111  inline int setBits(void) const { return _info.row_bits; }
112  inline int tagBits(void) const { return 32 - blockBits() + rowBits(); }
113  inline int wayBits(void) const { return _info.way_bits; }
114 
115  inline ot::mask blockMask(void) const { return blockSize() - 1; }
116  inline ot::mask setMask(void) const { return (rowCount() - 1) << blockBits(); }
117  inline ot::mask tagMask(void) const { return ~(lineMask() | blockMask()); }
118 
119  // Address decomposition
120  inline offset_t offset(Address addr) const { return ot::mask(addr.offset()) & blockMask(); }
121  inline set_t set(Address addr) const { return (ot::mask(addr.offset()) & lineMask()) >> blockBits(); }
122  inline tag_t tag(Address addr) const { return ot::mask(addr.offset()) >> (blockBits() + rowBits()); }
123  inline block_t block(Address addr) const { return ot::mask(addr.offset()) >> blockBits(); }
124  inline Address round(Address addr) const
125  { if(addr.isNull()) return addr; else return Address(addr.page(), addr.offset() & ~(blockSize() - 1)); }
126 
127  // Modifiers
128  void setAccessTime(int access_time);
129  void setMissPenalty(int miss_penalty);
130  void setBlockBits(int block_bits);
131  void setRowBits(int set_bits);
132  void setWayBits(int way_bits);
133  void setReplacePolicy(replace_policy_t replace);
134  void setWritePolicy(write_policy_t write);
135  void setAllocate(bool allocate);
136  void setWriteBufferSize(int write_buffer_size);
137  void setReadPortSize(int read_port_size);
138  void setWritePortSize(int write_port_size);
139 
140  // deprecated
141  inline int rowBits(void) const { return _info.row_bits; }
142  inline ot::mask lineMask(void) const { return (rowCount() - 1) << blockBits(); }
143  inline ot::mask rowMask(void) const { return (rowCount() - 1) << blockBits(); }
144  inline ot::mask line(const Address& addr) const { return (ot::mask(addr.offset()) & lineMask()) >> blockBits(); }
145  inline int rowCount(void) const { return 1 << rowBits(); }
146 };
147 
148 } } // otawa::hard
149 
152 
153 #endif // OTAWA_HARD_CACHE_H
Address round(Address addr) const
Round the given address to the address of the container cache block.
Definition: Cache.h:124
void setReadPortSize(int read_port_size)
Set the read port size (at least 1).
Definition: hardware_Cache.cpp:333
ot::size blockSize(void) const
Get the block size.
Definition: Cache.h:95
Definition: Cache.h:50
Definition: Cache.h:47
int read_port_size
Definition: Cache.h:60
virtual ~Cache(void)
Definition: hardware_Cache.cpp:41
t::uint32 mask
Definition: base.h:45
ot::mask tagMask(void) const
Mask for selecting the tag in a memory address.
Definition: Cache.h:117
enum otawa::hard::Cache::write_policy_t write_policity_t
write_policy_t write
Definition: Cache.h:57
int miss_penalty
Definition: Cache.h:52
t::uint32 offset_t
Definition: Cache.h:67
info_t _info
Definition: Cache.h:83
int tagBits(void) const
Required bits count in the tag part of the address.
Definition: Cache.h:112
const Cache * _next
Definition: Cache.h:84
void setMissPenalty(int miss_penalty)
Set the miss penaly time.
Definition: hardware_Cache.cpp:250
Definition: Cache.h:41
write_policy_t
Definition: Cache.h:45
void setReplacePolicy(replace_policy_t replace)
Set the replace policy of the cache.
Definition: hardware_Cache.cpp:293
int way_bits
Definition: Cache.h:55
int write_buffer_size
Definition: Cache.h:59
t::uint32 tag_t
Definition: Cache.h:66
Definition: Cache.h:40
ENUM(otawa::hard::Cache::replace_policy_t)
void setWriteBufferSize(int write_buffer_size)
Set the write buffer size (0 for no write buffer).
Definition: hardware_Cache.cpp:323
Definition: Cache.h:42
Definition: Cache.h:38
void setBlockBits(int block_bits)
Definition: hardware_Cache.cpp:261
void setWritePolicy(write_policy_t write)
Set the write policy of the cache.
Definition: hardware_Cache.cpp:303
bool isNull(void) const
Test if the address is null.
Definition: base.h:72
replace_policy_t
Definition: Cache.h:36
int missPenalty(void) const
Return the time penaly of a missed access to memory.
Definition: Cache.h:104
t::uint32 set_t
Definition: Cache.h:65
t::uint32 size
Definition: base.h:46
int wayBits(void) const
Get the number of bits to count the ways in set associative cache.
Definition: Cache.h:113
int setBits(void) const
Definition: Cache.h:111
Field< T > field(CString name, T &value)
ot::size cacheSize(void) const
Get the cache size.
Definition: Cache.h:94
ot::mask blockMask(void) const
Mask for selecting the address of a byte in a block in a memory address.
Definition: Cache.h:115
This class contains the configuration of a level of cache of processor.
Definition: Cache.h:34
offset_t offset(void) const
Get the offset value.
Definition: base.h:70
Cache(void)
Definition: hardware_Cache.cpp:28
The representation of an address in OTAWA.
Definition: base.h:54
void setAccessTime(int access_time)
Set the access time.
Definition: hardware_Cache.cpp:240
bool doesWriteAllocate(void) const
Set the behaviour about write allocation.
Definition: Cache.h:103
int readPortSize(void) const
Get the read port size of this cache (default to 1, must be non-null).
Definition: Cache.h:106
void setRowBits(int set_bits)
Set the row count as a number of bits.
Definition: hardware_Cache.cpp:272
ot::mask line(const Address &addr) const
Compute the line number from the memory address.
Definition: Cache.h:144
void setAllocate(bool allocate)
Set the allocation state.
Definition: hardware_Cache.cpp:314
StringOption cache(command, 'c',"cache","used cache","path","")
write_policy_t writePolicy(void) const
Get the write policy.
Definition: Cache.h:102
int blockCount(void) const
Definition: Cache.h:99
tag_t tag(Address addr) const
Compute the tag from the memory address.
Definition: Cache.h:122
struct otawa::hard::Cache::info_t info_t
int writePortSize(void) const
Get the write port size of this cache (default to 1 for data cache).
Definition: Cache.h:107
Definition: Cache.h:39
int rowCount(void) const
Get the count of rows.
Definition: Cache.h:145
void setWayBits(int way_bits)
Set the way count as a number of bits.
Definition: hardware_Cache.cpp:283
ot::mask lineMask(void) const
Mask for selecting the line number in a memory address.
Definition: Cache.h:142
bool allocate
Definition: Cache.h:58
int access_time
Definition: Cache.h:51
replace_policy_t replace
Definition: Cache.h:56
t::uint32 block_t
Definition: Cache.h:64
int block_bits
Definition: Cache.h:53
Definition: Cache.h:46
int rowBits(void) const
Required bits count for a row index.
Definition: Cache.h:141
int row_bits
Definition: Cache.h:54
int writeBufferSize(void) const
Get the write buffer size of this cache (0 for no write buffer).
Definition: Cache.h:105
replace_policy_t replacementPolicy(void) const
Get the replacement policy.
Definition: Cache.h:101
int blockBits(void) const
Required bits count for a byte address in the block.
Definition: Cache.h:110
const Cache * nextLevel(void) const
Get the next level of cache.
Definition: Cache.h:93
int setCount(void) const
Definition: Cache.h:98
SERIALIZABLE(Cache, field("access_time", _info.access_time, 1)&field("miss_penalty", _info.miss_penalty, 10)&field("block_bits", _info.block_bits, 4)&field("row_bits", _info.row_bits, 12)&field("way_bits", _info.way_bits, 0)&field("allocate", _info.allocate, false)&field("next", _next,(const Cache *) 0)&field("replace", _info.replace, LRU)&field("write_buffer_size", _info.write_buffer_size, 0)&field("read_port_size", _info.read_port_size, 1)&field("write_port_size", _info.write_port_size, 1)&field("write", _info.write, WRITE_THROUGH))
block_t block(Address addr) const
Return the bits used for identifying uniquely a block, that is, tag and line number.
Definition: Cache.h:123
Definition: Cache.h:37
ot::mask setMask(void) const
Definition: Cache.h:116
set_t set(Address addr) const
Definition: Cache.h:121
offset_t offset(Address addr) const
Compute the offset of the accessed byte in the block from the memory address.
Definition: Cache.h:120
ot::mask rowMask(void) const
Definition: Cache.h:143
int write_port_size
Definition: Cache.h:61
int wayCount(void) const
Get the count of ways for associatives caches.
Definition: Cache.h:97
page_t page(void) const
Get the page number.
Definition: base.h:69
uint32_t uint32
void setWritePortSize(int write_port_size)
Set the write port size (at least 1).
Definition: hardware_Cache.cpp:343