Otawa  0.10
Memory.h
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1 /*
2  * $Id$
3  * Platform class interface
4  *
5  * This file is part of OTAWA
6  * Copyright (c) 2008, IRIT UPS.
7  *
8  * OTAWA is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * OTAWA is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with OTAWA; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21  */
22 #ifndef OTAWA_HARD_MEMORY_H
23 #define OTAWA_HARD_MEMORY_H
24 
25 #include <elm/assert.h>
26 #include <elm/genstruct/Table.h>
27 #include <elm/string.h>
28 #include <otawa/base.h>
29 #include <elm/serial2/macros.h>
30 #include <elm/serial2/collections.h>
31 #include <elm/system/Path.h>
32 #include <elm/genstruct/HashTable.h>
33 #include <otawa/prog/Manager.h>
35 
36 namespace elm { namespace xom { class Element; } }
37 
38 namespace otawa { namespace hard {
39 
40 using namespace elm;
41 using namespace elm::genstruct;
42 
43 // ModeTransition class
44 class Mode;
46  SERIALIZABLE(ModeTransition,
47  field("latency", _latency) & field("power", _power) & field("dest", _dest));
48 public:
49  inline ModeTransition(void): _latency(1), _power(0), _dest(0) { }
50  inline int latency(void) const { return _latency; }
51  inline int power(void) const { return _power; }
52  inline const Mode *dest(void) const { return _dest; }
53 
54 private:
55  int _latency;
56  int _power;
57  const Mode *_dest;
58 };
59 
60 
61 // Mode class
62 class Mode {
63  SERIALIZABLE(Mode,
64  field("name", _name)
65  & field("latency", _latency)
66  & field("static_power", _static_power)
67  & field("dynamic_power", _dynamic_power)
68  & field("transitions", _transitions));
69 public:
70  inline Mode(void): _name("no name"), _latency(1), _static_power(0), _dynamic_power(0) { }
71  inline const string& name(void) const { return _name; }
72  inline int latency(void) const { return _latency; }
73  inline int staticPower(void) const { return _static_power; }
74  inline int dynamicPower(void) const { return _dynamic_power; }
75  inline const Table<ModeTransition>& transitions(void) const { return _transitions; }
76 
77 private:
78  string _name;
79  int _latency;
80  int _static_power, _dynamic_power;
82 };
83 
84 // Bank class
85 class Bus;
86 class Bank {
87 public:
88  typedef enum type_t {
89  NONE = 0,
90  DRAM = 1,
91  SPM = 2,
92  ROM = 3,
93  IO = 4
94  } type_t;
95 private:
96  SERIALIZABLE(Bank,
97  field("name", _name) &
98  field("address", _address) &
99  field("size", _size) &
100  field("type", _type) &
101  field("latency", _latency) &
102  field("power", _power) &
103  field("block_bits", _block_bits) &
104  field("modes", _modes) &
105  field("cached", _cached) &
106  field("on_chip", _on_chip) &
107  field("writable", _writable) &
108  field("port_num", _port_num) &
109  field("bus", _bus) &
110  field("write_latency", _write_latency));
111 public:
112  static Bank full;
113  Bank(void);
114  Bank(cstring name, Address address, size_t size);
115 
116  inline const string& name(void) const { return _name; }
117  inline const Address& address(void) const { return _address; }
118  inline const int size(void) const { return _size; }
119  inline type_t type(void) const { return _type; }
120  inline int latency(void) const { return _latency; }
121  inline int writeLatency(void) const { if(!_write_latency) return _latency; else return _write_latency; }
122  inline int power(void) const { return _power; }
123  inline int blockBits(void) const { return _block_bits; }
124  inline int blockSize(void) const { return 1 << _block_bits; }
125  inline const Table<const Mode *>& modes(void) const { return _modes; }
126  inline bool isCached(void) const { return _cached; }
127  inline bool isOnChip(void) const { return _on_chip; }
128  inline bool isWritable(void) const { return _writable; }
129  inline int portNum(void) const { return _port_num; }
130  inline const Bus *bus(void) const { return _bus; }
131 
132  inline Address topAddress(void) const { return address() + size(); }
133  inline bool contains(Address addr) const
134  { return addr.page() == address().page() && addr >= address() && addr <= (topAddress() - 1); }
135 
136 private:
137  string _name;
139  int _size;
141  int _latency, _power, _write_latency;
144  bool _cached;
145  bool _on_chip;
146  bool _writable;
148  const Bus *_bus;
149 };
150 
151 
152 // Bus class
153 class Bus {
154 public:
155  typedef enum type_t {
156  LOCAL = 0,
157  SHARED = 1
158  } type_t;
159 private:
160  SERIALIZABLE(Bus, field("name", _name) & field("type", _type));
161 public:
162  inline Bus(void): _name("no name"), _type(LOCAL) { }
163  inline const string& name(void) const { return _name; }
164  inline type_t type(void) const { return _type; }
165 
166 private:
167  string _name;
169 };
170 
171 
172 // Memory class
173 class Memory {
174 private:
175  SERIALIZABLE(Memory, field("banks", _banks) & field("buses", _buses));
176 public:
177  static const Memory null, full;
178  Memory(bool full = false);
179  virtual ~Memory(void);
180  inline const Table<const Bank *>& banks(void) const { return _banks; }
181  inline const Table<const Bus *>& buses(void) const { return _buses; }
182  static Memory *load(const elm::system::Path& path) throw(LoadException);
183  static Memory *load(xom::Element *element) throw(LoadException);
184  const Bank *get(Address address) const;
185  int worstAccess(void) const;
186  int worstReadAccess(void) const;
187  int worstWriteAccess(void) const;
188 
189 private:
192 };
193 
194 // features
197 
198 } // hard
199 
201 
202 } // otawa
203 
206 namespace elm { namespace serial2 {
207  void __serialize(elm::serial2::Serializer &serializer, const otawa::Address& address);
208  void __unserialize(elm::serial2::Unserializer &serializer, otawa::Address& address);
209 }}
210 
211 #endif // OTAWA_HARD_MEMORY_H_
The usual Feature class has as drawback to exhibit completely the processing of the feature and there...
Definition: SilentFeature.h:32
Mode(void)
Constructor with default initialization:
Definition: Memory.h:70
AllocatedTable< const Bank * > _banks
Definition: Memory.h:190
int _static_power
Definition: Memory.h:80
int dynamicPower(void) const
Get the dynamic power consumed by this memory.
Definition: Memory.h:74
Identifier< const Memory * > MEMORY
Current memory.
const Bus * _bus
Definition: Memory.h:148
type_t
Type of used bus.
Definition: Memory.h:155
int latency(void) const
Get the latency of the transition.
Definition: Memory.h:50
int blockSize(void) const
Get the block size of this bank.
Definition: Memory.h:124
ModeTransition(void)
Build a default transition mode with :
Definition: Memory.h:49
type_t _type
Definition: Memory.h:168
Address topAddress(void) const
Get the top successor address of the bank, that is, bank address + bank size.
Definition: Memory.h:132
Definition: ClpValue.h:54
static const Memory null
Default null memory.
Definition: Memory.h:177
type_t type(void) const
Get the type of the bank.
Definition: Memory.h:119
int _power
Definition: Memory.h:56
int portNum(void) const
Get the number of port on the bank bus.
Definition: Memory.h:129
int writeLatency(void) const
Definition: Memory.h:121
const Bus * bus(void) const
Get the bus of the bank.
Definition: Memory.h:130
static Bank full
The full covering all page one memory.
Definition: Memory.h:112
int power(void) const
Get the default power for accessing this bank.
Definition: Memory.h:122
int _size
Definition: Memory.h:139
Address _address
Definition: Memory.h:138
Class to represent the whole memory of the platform.
Definition: Memory.h:173
uint32 size
elm::io::IntFormat address(Address addr)
Build a format to display addresses.
Definition: base.cpp:213
const Table< ModeTransition > & transitions(void) const
Get the mode transition table (may be empty).
Definition: Memory.h:75
int _latency
Definition: Memory.h:79
A bus that tie together several memory banks.
Definition: Memory.h:153
type_t
This type represents the type of banks:
Definition: Memory.h:88
int _block_bits
Definition: Memory.h:142
io::Output & operator<<(io::Output &out, const Platform::Identification &id)
Definition: Platform.h:140
const Mode * dest(void) const
Get the destination mode of the transition.
Definition: Memory.h:52
Field< T > field(CString name, T &value)
AllocatedTable< const Bus * > _buses
Definition: Memory.h:191
bool _cached
Definition: Memory.h:144
const int size(void) const
Get the size of the bank.
Definition: Memory.h:118
inst load(int d, int a, int t)
Definition: inst.h:153
bool isWritable(void) const
Test if the bank is writable.
Definition: Memory.h:128
The representation of an address in OTAWA.
Definition: base.h:54
Bus(void)
Default bus building:
Definition: Memory.h:162
AllocatedTable< ModeTransition > _transitions
Definition: Memory.h:81
Representation of a memory bank transition.
Definition: Memory.h:45
const Mode * _dest
Definition: Memory.h:57
int blockBits(void) const
Get the number of bits in the block size of the bank.
Definition: Memory.h:123
int staticPower(void) const
Get the static power consumed by this memory.
Definition: Memory.h:73
const string & name(void) const
Get the name of the bank.
Definition: Memory.h:116
ENUM(otawa::hard::Bus::type_t)
int power(void) const
Get the power consumed by the transition.
Definition: Memory.h:51
bool isCached(void) const
Test if the bank is cached.
Definition: Memory.h:126
bool contains(Address addr) const
Test if the address is contained in the bank.
Definition: Memory.h:133
SilentFeature MEMORY_FEATURE
This feature ensures we have obtained the memory configuration of the system.
A working mode for the hardware memory.
Definition: Memory.h:62
This class represents identifier with a typed associated value.
Definition: Identifier.h:51
const Table< const Mode * > & modes(void) const
Get the mode transition table of the bank.
Definition: Memory.h:125
int _write_latency
Definition: Memory.h:141
int _latency
Definition: Memory.h:55
AllocatedTable< const Mode * > _modes
Definition: Memory.h:143
cstring name
Definition: odisasm.cpp:107
Exception thrown when a loader encounters an error during load.
Definition: Manager.h:52
A bank in the memory.
Definition: Memory.h:86
int latency(void) const
Get the default latency for accessing this bank.
Definition: Memory.h:120
bool _writable
Definition: Memory.h:146
const Table< const Bank * > & banks(void) const
Get the list of banks in memory.
Definition: Memory.h:180
bool isOnChip(void) const
Test if the bank is on the same chip than the processor.
Definition: Memory.h:127
const Table< const Bus * > & buses(void) const
Get the list of buses connected to memory banks.
Definition: Memory.h:181
int latency(void) const
Get the latency to access the memory in this mode.
Definition: Memory.h:72
const string & name(void) const
Definition: Memory.h:163
bool _on_chip
Definition: Memory.h:145
string _name
Definition: Memory.h:167
string _name
Definition: Memory.h:137
page_t page(void) const
Get the page number.
Definition: base.h:69
type_t type(void) const
Definition: Memory.h:164
const Address & address(void) const
Get the base address of the bank.
Definition: Memory.h:117
type_t _type
Definition: Memory.h:140
const string & name(void) const
Get the mode name.
Definition: Memory.h:71
type_t
Definition: features.h:57
string _name
Definition: Memory.h:78
int _port_num
Definition: Memory.h:147