22 #ifndef OTAWA_DCACHE_ACSBUILDER_H_
23 #define OTAWA_DCACHE_ACSBUILDER_H_
39 inline Domain(
const int _size,
const int _A):
ACS(_size, _A, 0) { }
58 inline void addDamage(
const int id,
const int damage) {
59 ASSERT((
id >= 0) && (
id <
size));
69 for (
int i = 0; i <
size; i++) {
70 if ((age[i] < age[
id]) && (age[i] != -1))
74 for (
int i = 0; i <
size; i++) {
84 for (
int i = 0; i <
size; i++) {
98 const Domain& bottom(
void)
const;
101 for (
int i = 0; i <
size; i++)
102 if (((a[i] < b[i]) && (a[i] != -1))|| (b[i] == -1))
132 virtual void configure(
const PropList &props);
dtd::RefAttr< BasicBlock * > source("source", dtd::STRICT|dtd::REQUIRED)
A block access represents a data memory access of an instruction.
Definition: features.h:125
int set
Definition: ACSBuilder.h:116
bool equals(const ACS &dom) const
Test if two ACS are equals.
Definition: features.h:61
This builder performs analysis of the L1 data cache and produces ACS for MUST and, according to the configuration proerties, persistence.
Definition: ACSBuilder.h:127
Domain(const int _size, const int _A)
Definition: ACSBuilder.h:39
void assign(Domain &a, const Domain &b) const
Definition: ACSBuilder.h:105
Definition: ACSBuilder.h:37
Class to declare simple a processor.
Definition: Registration.h:213
Domain callstate
Definition: ACSBuilder.h:94
void addDamage(const int id, const int damage)
Definition: ACSBuilder.h:58
dtd::Element bb(dtd::make("bb", _BB).attr(id).attr(address).attr(size))
elm::io::Output & operator<<(elm::io::Output &out, Address addr)
Definition: base.cpp:188
Domain(const ACS &source)
Definition: ACSBuilder.h:41
Domain bot
Definition: ACSBuilder.h:118
The processor class is implemented by all code processor.
Definition: Processor.h:49
Domain ent
Definition: ACSBuilder.h:119
void leaveContext(Domain &dom, BasicBlock *header, util::hai_context_t ctx)
Definition: ACSBuilder.h:112
genstruct::Vector< ACS * > * must_entry
Definition: ACSBuilder.h:138
dtd::Element entry(dtd::make("entry", _ENTRY).attr(id))
A workspace represents a program, its run-time and all information about WCET computation or any othe...
Definition: WorkSpace.h:67
const hard::Cache * cache
Definition: ACSBuilder.h:117
This class contains the configuration of a level of cache of processor.
Definition: Cache.h:34
bool equals(const Domain &a, const Domain &b) const
Definition: ACSBuilder.h:107
Domain & operator=(const ACS &d)
Definition: ACSBuilder.h:42
bool unrolling
Definition: ACSBuilder.h:137
void ageAll(void)
Definition: ACSBuilder.h:83
sys::SystemOutStream & out
void enterContext(Domain &dom, BasicBlock *header, util::hai_context_t ctx)
Definition: ACSBuilder.h:111
hai_context_t
Definition: HalfAbsInt.h:50
void lub(Domain &a, const Domain &b) const
Definition: ACSBuilder.h:100
This is the minimal definition of a basic block.
Definition: BasicBlock.h:43
static p::declare reg
Definition: ACSBuilder.h:129
data_fmlevel_t level
Definition: ACSBuilder.h:136
This a list of properties.
Definition: PropList.h:63
The MUST problem provides the abstract interpretation of L1 data cache for the MUST case...
Definition: ACSBuilder.h:35
Domain(const Domain &source)
Definition: ACSBuilder.h:40
Representation of an Abstract Cache State where each data cache block is represented by its age...
Definition: features.h:47
data_fmlevel_t
Definition: features.h:38
void inject(const int id)
Definition: ACSBuilder.h:67
int size
Definition: ACSBuilder.h:120
A block collections stores the list of data blocks used in a task for a specific line.
Definition: features.h:108
void assign(Domain &a, const ACS &b) const
Definition: ACSBuilder.h:106
WorkSpace * fw
Definition: ACSBuilder.h:115